The present invention relates generally to an analog receiver circuit for providing a DC-centered analog signal to a flash A/D converter. More particularly, the invention relates to an analog receiver circuit for receiving a time-varying read signal from a disk drive, and for dynamically centering the read signal with respect to the DC operating point of a flash A/D converter.
"Flash" A/D converters are well-known in the art and are described in U.S. Pat. No. 4,608,555 issued to Hoeft, which contains additional references on the subject. Flash A/D converters are typically VLSI circuits able to perform rapid, high resolution analog to digital conversions via a simultaneous or "parallel" processing architecture.
A flash A/D converter usually includes an array of comparators and their associated drivers, a resistor ladder with a current source, and an encoder. The comparators simultaneously receive an analog signal input to the converter. Additionally, each comparator is provided with a unique reference voltage from the resistor ladder corresponding to one of N possible converter output states. The outputs of the comparators are coupled to the encoder inputs, and the encoder outputs in turn provide the flash A/D converter output.
The converter design just described is sometimes called a "full flash" A/D converter because all bits are processed simultaneously for one analog input sample. Consequently, this design requires a large number of comparators on a single chip. Alternate designs have been developed to reduce the circuit size by breaking down the processing into cycles. A half-flash A/D converter is described in U.S. Pat. No. 4,639,715 to Chin which performs two processing cycles for every analog input sample, using a lower resolution flash A/D converter. In a first cycle the converter processes the higher-order bits, and in the second cycle it processes the lower-order bits. A pipelined A/D converter such as that described in U.S. Pat. No. 4,894,657 to Hwang et al. uses several processing stages to perform one conversion, each stage comprising a low-resolution flash A/D converter. The disadvantage of these alternate designs is their reduced operating speed.
An n-bit resolution full-flash A/D converter generally includes (2.sup.n -1) comparators corresponding to each possible state of an n-bit output (except zero). The resistor ladder has (2.sup.n -1) taps for providing (2.sup.n -1) unique reference voltages. The encoder has (2.sup.n -1) inputs, coupled respectively to the comparator outputs. Each encoder input corresponds to a unique state of the n-bit output (except zero). Thus the output of the converter will be determined by a high state on one of the comparator outputs (or zero if no input is turned "on").
During operation, an input analog signal is provided to each comparator and is simultaneously compared to each of the (2.sup.n -1) reference voltages, and will cause all the comparators having a reference voltage below or equal to the analog voltage to turn "on". The active comparators are detected by the encoder, which selects an appropriate corresponding output state.
The DC reference voltages of the resistor ladder become smaller as the resolution of the converter increases. This constraint is imposed by the voltage swing of an analog signal, which is generally 2 V or less. The higher the resolution, the smaller the increments into which this voltage range must be divided to represent the number of possible output states.
To perform accurate conversions it is therefore necessary to assure that the flash A/D converter receives an analog signal which is centered with respect to the converter's operating point voltage, which is available at the centertap of the resistor ladder.
In previous designs, the analog signal has been provided to the flash A/D converter by an amplifying receiver. The analog signal is provided to an amplifying circuit such as an operational amplifier. The op amp, in turn, produces an amplified analog signal which is centered with respect to the operating point voltage of the flash A/D converter. DC-centering is achieved by using a current mirroring configuration within the op amp. The converter's operating point voltage is provided via the centertap to the current mirroring circuit. The current mirroring circuit then "mirrors" the centertap voltage internally, thereby establishing the amplifier's own operating point.
A disadvantage of the previous designs is the substantial bandwidth limiting introduced by the amplifying circuit. Since the analog signal is both amplified and DC-centered in one stage, the signal passes through a number of bandwidth-limiting circuit elements before it reaches the converter. Consequently, the system response time of the receiver is reduced, rendering the design impractical in systems which operate at frequencies of 500 MHz and greater.
Other disadvantages of the previous designs relate to DC offsets. As previously discussed, the amplifying circuit is designed to receive the centertap voltage of the flash A/D converter, and to replicate this voltage internally. In theory, the elements of the current-mirroring circuit are identically matched to provide an amplifier operating point exactly equal to that of the converter. But in practice, precise matching is difficult to achieve because of technology limitations. Thus each element of the receiver may introduce a slight DC offset to the analog signal passing through. By the time the signal reaches the converter, its DC offset may be quite large. Such a design is unsatisfactory for converters having low offset requirements. Furthermore, the operational amplifier used in previous designs must provide high gain to minimize offset. A high gain amplifier design is more complex than low gain designs.
Yet another limitation of past designs arises when the centertap reference voltage drifts over time. The current mirror response to such changes tends to be slow, causing a significant offset in the analog signal provided to the converter input until the receiver stabilizes.
Finally, past designs have the disadvantage of poor noise immunity. Present signal-processing chips often comprise a combination of analog and digital components. The digital elements tend to inject a large amount of noise into the system. The amplifying receiver described further degrades the signal to noise ratio, and adversely affects the system error rate.
An attempt has been made to improve the system response time of previous designs by providing both positive and negative voltage sources to the op amp rather than using a single 5 V supply. This modification, however, leads to other problems of high cost, poor technology reliability and complex implementation.
The rapid conversion rate of flash A/D converters is particularly valuable in a variety of applications, including digital magnetic recording channels, cellular phones and satellite communication systems.
What is needed is an analog receiver with minimal buffering introduced between the input and output analog signals, permitting operation at frequencies of 500 MHz or greater with minimal DC offset. Furthermore, the analog receiver must be able to continually track the centertap voltage of the flash A/D converter in order to maintain an operating point substantially equal to the converter's operating point, thus providing a DC-centered analog signal to the converter having minimal DC offset over time. Ideally, the DC offset should be less than 1/2 of the converter's least significant bit (LSB) reference voltage, since a greater offset can cause a false bit-reading or failure to detect a bit due to the signal displacement with respect to the converter operating voltage. The analog receiver must not degrade the signal-to-noise ratio of the system to any significant extent.